Let's talk about Telum.
First of all, Telum is not z16. It is a new generation that shows some traces of power, but it is not entirely power. Telum leans towards its banking and encryption needs.
And the important thing to discuss is the design of the cache.
Telum has eliminated L3 and L4 and replaced them with a huge L2. This design leads to a significant access latency in the cache. However, Telum is quite amazing. It places the data that used to be stored in L3 in the remaining unused cores' L2, and the same goes for L4. This means that, in a sense, a chip physically has a 256M L2 (8X32), but a single core can read the 32M L2 outside the core, 256M L3, and the entire complex (the entire IBM z16? unit) of 32mx8 cores x2 (2 dies packaged in one sub) x16 of 8GB L4. To put it simply, if a core's data cannot fit, it can be placed in the L2 of other cores, different substrates, or even different groups or units, as long as they are available.
This is... quite strange? But this is also the future of caching.
There is not much to talk about other cores, as they have many vulnerabilities. Just bear with it.
4-channel DDR5 x8x4 PCIe 5.0, a bunch of AI encryption units...
The IBM Telum Dieshot drawing, image from the IBM official website, made/drawn by Kurnal.
Reprinting instructions: Just mention that the drawing is from Kurnal.