This article is an analysis of Hi36a0V120
This article was written three days after the release of Mate60, with an unknown publication date.
Overview#
Hi36A0V120, internally codenamed Charlotte
CPU: TSV120+TSV120+A510
SUB: Self-developed bus
GPU: Maliang 910
NPU: Iterative, should still be Da Vinci NPU, 1b+1l design
Modem: No specific name, but it can be seen from the Dieshot that it has no PCIe, indicating that its baseband is integrated
Manufacturing process is Smic7
Decap Analysis#
First, we are using the Die provided by Gugugu, disassembled from a newly purchased Mate60Pro
It is clearly a pop package
The Top Package is Hynix particles
Blowing down reveals
Topmark is
Hi36A0
GFCV120
JTFQ3T0V1
2035-CN09
06
DataCode (TOP Marking) Analysis#
HiSilicon: HiSilicon Semiconductor
Hi36A0 indicates the Hi36 product line, A0 indicates the product is the tenth generation (123-9ABCD…)
The 1 in V120 indicates the product generation (for example, the first generation V100 and the second generation V200 for televisions) in the Hi36 series, only Hi3690 has V100/V200, which is a dual scheme, the meaning is uncertain
2 indicates a design GDS version change, generally optimized gradually after mass production, like hi6260v131
0 indicates minor optimizations, the rest shows no discernible pattern
2035CN theoretically indicates the packaging date, 09 is the code for factory packaging
The X-ray image shows it is a FanOut Package
So, X-ray it is
X Ray#
The X-ray clearly shows it is a FanOut Package
The three black dots on the edge are the bump points connecting the Top Package and Bottom Package, but it is strange that they are not seen in the physical image, not on the same layer of the package, possibly indicating the use of other manufacturers' flash chips later (saving the time for repackaging?)
It may also be the wiring inside the Bottom Die
The edge clearly shows the connection bonding points between the Die and the edge IO PHY layer, allowing for an estimated Die Size of about 10x10.
These are the data that can be seen from the X-ray image, indicating that it has been decapped.
Decap#
Decapping
After decapping, it can be seen
Its Diemark is suspected to be HL 02 20210603, which means it was produced on June 3, 2021.
This is a very strange number
Because the outer packaging is 2035cn
Its internal actual production date is 20210603, I believe the topmark 2035CN is a disguise, or even fixed.
No other suspected Diemark was found anywhere.
Unlike previous Kirin versions which used Hixxxx Vxxx version numbers, it is not directly visible.
It is impossible to determine the specific product code/version stage (for example, is it actually Hi36A0/Hi36B0?)
I believe this product belongs to an entirely new generation, rather than a simple V120 version stepping iteration, but rather a completely new product, of course, without sufficient evidence to support my view.
Alignment System Analysis#
Three alignment systems were observed on the edges,
Proving that some production line equipment is ASML's stepper lithography machine
The marks are automatically recognized alignment marks through overlay measurement equipment
Line overlay marks (Bar in Bar mark)
Line overlay marks (Bar in Bar mark)
AIM overlay marks
AIM overlay marks
Suspected Canon alignment system (i-line and KrF)
The most important thing is this alignment system
In this image
You can see the regular vertical stripes, one group has 9 stripes, another group has 8 stripes, each stripe has 4 evenly spaced vertical stripes.
This clearly indicates that the most advanced alignment system used by this chip is
ASML's Athena alignment system
Among them, this stripe belongs to the Versatile Scribeline Primary Mark (VSPM) AH74
This alignment system is only used in ASML equipment
AH74 is even rarer, available in 1960-2000i.
Now that we know the manufacturing equipment, we can calculate its capacity and yield.
Capacity Analysis#
According to known information, SMIC has about two NXT1980di, but allocated 60% of the capacity to Huawei with an 80% utilization rate +40 DUV mask calculation.
The formula is: 550wph x 24h x 60% x 80% / 40 = 158.4 Wafer
This Die was produced in June 2021.
From production until now, it is September 1, 2023.
It is uncertain if there are earlier Dies, but this is currently the earliest Die, so we calculate it.
The total production time is approximately 822 days, excluding possible rest days, about 800 days of production,
800 x 158.4
which is 126,720 Wafer.
Yield Analysis#
Now we calculate the yield.
Internal sources indicate that this wafer has approximately 300 pieces of Die cut.
The known Die size is 10.7x10.4, we need to find Yield.
Dpw can be calculated.
D0 is approximately 0.6, between 0.6-0.55, yield is 53.22%.
By this year, the yield ramp-up is about 0.3.
Using a linear graph to find the midpoint, assuming uniform ramp-up.
At 400 days, D0=0.45, which means 350 Good Die, yielding 61.88%.
When D0=0.3
At 800 days, D0=0.3, which means 409 Good Die, yielding 72.28%.
For convenience, the median is D0=0.45.
126720 x 566 x 61.88% = 44,382,514.176
Thus, the estimated number is that Huawei produced 40-45 million pieces of Hi36a0V120, roughly calculated.
Die Markings#
Searching within the Die, there are a few more points,
For example, F-shaped stripes
B+ numbers, marked areas/test points
IO PHY
This image clearly shows the points on the edge for fan-out.
There is also a very strange silkscreen
2017 Mora
A?C?E?A?
A 01 0
Not very clear what it is suspected to be
Week 17 of 2020, must it be?
Must be 2017?
Very strange.
There is also an sa06 with a cross alignment mark on the left.
Removing Metal Layers#
Next is the removal of metal layers.
Since the wiring is Cu, it is acid-etched.
Acid etching will have a scrap rate, but this time it was very lucky, perfect.
Very beautiful, now we proceed to
Dieshot Layout#
It is clear that
First, it can be determined that this chip is not the same as Kirin 9000, it is not the same product.
I also did Kirin 9000.
Making a comparison
It is evident that these two are not the same chip
Because the Die shapes are different, the overall scale is similar,
Indicating that Hi36A0 V100 and Hi36A0V120 are completely different, not just a skin swap/stock.
This completely proves that Kirin 9000s does not belong to a structure similar to 9000L/9000e skin swap,
Nor does it belong to a partially shared design structure like 985/990.
Rather, it is an entirely new generation, with no identical parts.
Thus, the analysis is complete.
CPU#
First, the comparison of the CPU
You can see the huge area of the CPU Cluster, which has undergone significant changes compared to the previous generation.
On the left is TSMC N5 A77+A77+A55, 134
On the right is SMIC N7 TSV120+TSV120+A510, 134
Comparison of the size of the super-large core
The area has increased… a significant increase.
Performance analysis not written#
No L0 Cache
The architecture is too wide, requiring cache.
Regarding the small core, it is A510, a dual-core composite at 1.53GHz, at the optimal sweet spot frequency, while under TSMC process it is 1.4GHz.
Additionally, this generation's bus does not use the performance library like the previous generation's bus and super-large core.
This generation only the super-large core uses the performance library,
The color change is due to
I believe it is the density of the poly layer transistors causing the change in reflective spectrum.
GPU Analysis#
The previous generation Mali G78 Mc24 is a typical stacked material.
Mali G78 is based on the Valhall architecture, mc24 indicates it has 24 cores.
Its GPU is a core design,
While this generation's Maliang is a CU design,
Its design scale is slightly smaller than the previous generation.
The unit division is as shown.
It has 4 CUs,
Two groups of ALU Cores on the left and right, each group has 128 ALUs, totaling 2x4x128 ALUs = 1024 ALUs.
The maximum frequency is 750MHz, with a theoretical performance of 1536 Gflops.
The middle part is the GPU L2 Cache, approximately 1 MiByte.
From the specifications of its GPU,
It is not the same as common IMG/MALI/Adreno/Rdna/Cuda.
I believe this is a completely new self-developed GPU.
NPU#
In this generation's NPU,
The previous generation had dual large cores + 1 small core NPU, with each large core having two vectors.
This generation has a single large core + 1 small core NPU, with the large core having two slightly longer vectors.
From a macro perspective, I believe that although the scale has reduced by one large core, due to microarchitecture updates, performance may be enhanced, but the core scale reduction is a fact, saving a significant area for other units.
ISP#
The scale of the ISP has clearly increased compared to the previous generation ISP 6.0, but the common core of these two ISPs can be found.
In the center, there seems to be a newly added dual-core co-processor.
The theoretical image processing speed has increased; this generation's Mate60pro can perform HDR Vivid in the viewfinder and smoothly switch during zooming, which is due to the increased ISP computing power.
This ISP runs at mid-frequency, 2W, extremely terrifying.
DSP#
There isn't much to say about the DSP.
Nothing much can be seen; compared to the previous generation's Decode, it seems to have one less unit.
The area has shrunk a little.
Baseband#
In the baseband,
This generation's design is completely different from the previous Balong 5000.
Its area has significantly reduced.
Previously, Huawei's 5G baseband was always designed as 4G + 5G, with an interconnection bridge for data transmission.
Some external basebands, such as 990 4G, used PCIe x8+x16 for data transmission, then connected to Balong 5000.
In this generation's modem design, it is a pure Balong Baseband Modem System, integrating 4G and 5G, allowing for shared DSP and modem, eliminating the need for separate designs.