This should be the most detailed interpretation of the Kirin 9000 (third-party). Although Techinsights seems to have an analysis of this chip as well.
This is an estimate.
However, I personally think the price is too expensive, and I am obsessed with Dieshot, so I wrote this.
Below is the main text.
In early December 2022, I purchased several engineering samples of Hi36A0, equipped with SMIC self-packaged flash memory and demonstration substrates.
There is also a HimFOP (Hi Mechanical sample Fan Out Package),
After opening, it is pure silicon.
This is just a side note.
## Main Text
Hi36A0 is the Kirin 9000, Kirin 9000.
The official release date is October 22, 2020, released in week 42 of 2020.
According to the information I have found so far,
CS-ES-HVM total time is 1938TW-2038TW,
After 2021, it is packaged by ?, and the HVM time is unknown.
Among them, 1938TW is what I saw on Xianyu, existing, ah, and proves its production cycle. Unfortunately, I didn't have enough money to make a purchase.
Image Pigeon
The only existing ones I have are 1952TW and 2037TW.
Chip Analysis#
In early December, I purchased several engineering samples of Hi36A0, equipped with self-packaged flash memory.
It is a pop package, so I used a hot air gun to blow down the BGA to obtain the die of Hi36A0.
## Marking Number Analysis
The marking number is
HISILICON-HI36A0-GFCV010-HR1381952-1952TW 01 01
The interpretation of this marking is
HiSilicon Kirin - Chip Code - Version Number - Manufacturer/Equipment Production Line/Time - Packaging Time
HISILICON: HiSilicon Kirin
Hi36A0: The previous generation 990 is HI3690, which is the generation code.
GF CV010: CV010 indicates that this chip is a pre-production sample (Engineering Sample), while the official version's GDS version (normal machine) is generally GF CV100. Changing the GDS version indicates that the chip's design layout has changed. For example, HI3690V100/HI3690V200 corresponds to 990 4G/990 5G, and the internal marking is the same as the external version marking.
HR1381952 can be split into
HR: Fab, speculated to be TSMC Fab18
(H is the Fab code, R should be the production line code. The following is an estimated naming:
(H, Y, G, C, D) (D, P, R)
H: TSMC FAB18
Y: TSMC FAB15
G: TSMC FAB14
CD (SMIC: Shanghai/SN1)
138: Production line/machine/batch/chip orientation map?
1952: Week 52 of 2019 exposure.
1952TW: Produced in Taiwan in week 52 of 2019.
Decap Data#
This is the data you can see on the surface; deeper research requires Decap.
I happen to have contacts with a decapping company, so I proceeded with it.
I obtained several images.
Metal layer electron microscope photography
Metal layer metallographic microscope photography
Taken with an electron microscope after decapping.
You can clearly see the Diemark.
HI36A0 GFCV010 is the HI36A0 V100 ES version.
Diemark Analysis
When Huawei designs internal chips, they generally conduct CS iterations in dual versions, CS1, CS2. For example, HI3690V100 is CS1, and Hi3690V200 is CS2.
The development code name for Kirin 9000 is Baltimore,
The version number V100 indicates it is the CS1 scheme.
This indicates that the chip's Top Mark: GFCV010 corresponds to Baltimore CS1 V100ES.
So I opened other dies.
This product corresponds to Baltimore CS1 V100CS.
As shown in the figure, this model is a Huawei engineering machine, and the etching on the engineering machine's frame is AN00E-V4-B2, which was originally intended for Mate40Epro.
Analysis
AN00: Mobile version
E: Cut-down (with Q, T/M, E: Q: Qualcomm T/M (forgot which version) is MTK, E is cut-down)
V4: V version mark 4, later versions are VN.
Alignment System Analysis#
This image shows the self-alignment mark (TTL? TSA? TIS?) of the machine (manufacturer uncertain), possibly Athena (advanced technology using high order enhancement of alignment).
The regular crack white circles are Bump points, which are reserved solder points leading to Fan Out.
This image is important. This image TL5115H(TLS1SSH?) on the right has some regular stripes composed of evenly spaced lines rotated 45 degrees.
It is clear that this indicates the ASML Smash (Smart Alignment Sensor Hybrid) technology. The width of this alignment mark is 38um (expandable), and the length is 160um. The advantage of this technology is that it only requires one scan to obtain the X/Y axis position deviation resolution of the Wafer-Mask.
This device significantly improves the alignment speed/efficiency of the machine, although advanced processes seem to require Orion.
This allows us to determine that the alignment system used by TSMC is Smash, and this product is used in EUV.
SEM Report#
These are the initial observations from Decap. We amateurs are limited to this.
So the next step is SEM?
SEM Pigeon.
Dieshot Analysis#
Since acid etching has been performed,
we can completely conduct a Dieshot drawing.
Although there are already Dieshots and preliminary layouts of the Kirin 9000 on the market,
since we are doing it, we should do it well, so we will make a rough drawing and refine it.
There’s nothing much to say, just like this.
Capacity Calculation#
Based on TSMC's public information,
we conduct a production line estimate.
A single 3400B machine has a maximum exposure of 155 times/h.
In one day, that is 3720 exposures.
It is known that N5 EUV in Kirin 9000 requires about 12-15 EUV Wafers among 90 Mask wafers, _ (although N5 is 81 Masks (generally (69 193i masks + 11-13) EUV masks converted to EUV, which means originally 5 DUV masks, but the problem is that this is only in the best case, actual use will not be like this)_
The formula is _ (3720/(12~15)_
Thus, a single 3400B running at full capacity produces about 310~248 Wafers per day.
Also:
At the beginning of April, the monthly production was 30K,
and later increased to 50K from June to August.
(Update: I asked an insider, it was about 20k (February) - 25k (March) - 30k (April) - 35k (May) - 40k (June) - 45k (July) - 50k (August), just an estimate)
The formula is Production Capacity/(Machines x Days) = 100% operating rate, x actual operating rate.
In the case of monthly production of 30k Wafers:
Operating Rate 50%
3 0000/(248x30)=4.0322580 machines
50% operating rate = 8.064516 3400B machines can be used
3 0000/(310x30)=3.22580 machines
50% operating rate = 6.45161290 3400B machines can be used
In the case of monthly production of 50k Wafers:
Operating Rate 50%
5 0000/(248x30)=6.720
50% operating rate = 13.440860 machines
5 0000/(310x30)=5.3763440
50% operating rate = 10.7526881 machines
Operating Rate 60%
5 0000/(248x30)=6.720
60% operating rate = 11.200 machines
5 0000/(310x30)=5.3763440
60% operating rate = 8.960 machines
Later, the monthly production increased to 50K, which means an additional 3-5 3400B machines.
So what about the 5k wafer difference?
That is
5000/(248X30)=0.6720
50% = 1.3440860 machines
5000/(310X30)=0.53763440
50% = 1.07526881 machines
This means that each month, an additional 5k production capacity corresponds to an additional 1-1.5 HVM 3400B production line in that month.
This indicates that,
in April 2020 (around), there were about 6~8 3400B HVM production lines (30k).
In June to August 2020 (around), an additional 3~5 3400B HVM production lines were added (45k).
From February to September 2020, an average of 1-2 3400B HVM production lines were added each month (5k-7.5k).
This information is not available on the domestic internet because it is data confidentiality; I calculated it based on my own data.
TIPS:
Why only EUV was calculated: Because not all Masks in a Wafer production process are advanced processes. Generally, only Resistors, Metal/Via layers 0-3 use advanced processes, while the rest are generally ArF 193 (and even some KrF 248 or Hg i Line 365).
Why LELE was not calculated: Because LE is counted as one Mask in the EUV Mask.
Yield Calculation#
The following calculations are all based on
the line width of 0.08mm,
edge exclusion of 0mm,
Poisson model.
Currently, in TSMC's engineering research phase, there are two types of TEST Die:
A: 256Mib SRAM + Logic + IO Block (17.92 mm²) calculated as 4x4.48
B: 512Mib SRAM (9.891 mm²) calculated as 3x3.297
It is known that the average yield is 80%, and the peak yield is 90% (forgot where I saw this).
Calculation formula:
To find TSET D0:
A's D0 is
1.25 (80.27%) stands for A1 80% Yield
0.6 (89.89%) stands for A2 90% Yield
B's D0 is
2.3 (80.00%) stands for B1 80% Yield
1.1 (89.78%) stands for B2 90% Yield
Now, calculating based on the Kirin 9000 Die size of 10x10.6,
it can cut 596 dies.
Substituting D0:
A1:
D0=1.25
Yield=30.7% 183/596
A2:
D0=0.6
Yield=54.75% 326/596
B1:
D0=2.3
Yield=14.01% 84/596
B2:
D0=1.1
Yield=34.86% 208/596
Using the theoretical highest yield numbers,
the peak is D0=1.1,
Yield=34.86% 208/596.
The average is: D0=1.25,
Yield=30.7% 183/596.
Isn't that high? That's because we haven't discussed DTCO... If we include DTCO, the complexity of the calculation is very high, so we won't include it, just a hint.
Thus, the data indicates that in May 2020, the yield was approximately around 40%, and by September 15, 2020, it was around 45%.
2020 05: D0=0.95 Yield=39.72% 237/596
2020 0915:
D0=0.81 Yield=45% 268/596
It is evident that D0=1.25-1.1 was in November 2019.
This means that in May 2020, there was a significant yield ramp-up or an increase in operating rate.
Now, including capacity analysis,
the product capacity Die =
Number of dies that can be cut from a wafer x Yield x (Machine exposure times/Wafer required masks) x Operating rate x Number of devices x Production time hours x Production share ratio.
Total capacity = Number of devices x Production time/Wafer required masks x Operating rate x K1 (for example, droplet generator).
Thus, the product capacity Die number =
Total capacity/Allocated capacity x MPW x Yield.
Total capacity = DPW * Yield * (Exposure per hour/Exposure times) * Operating rate * Number of machines * Production time * Allocated capacity * K1 process factor: (DTCO x droplet generator long-term working efficiency).
The results are as follows:
2020 02: 596 x 35% x (155/15) x 50% x 4 x 696 x 40% x 85% x 80% = 816136.6528
2020 03: 596 x 37% x (155/15) x 50% x 6 x 744 x 40% x 85% x 80% = 1383411.93216
2020 04: 596 x 38% x (155/15) x 50% x 7 x 720 x 40% x 85% x 80% = 1604130.6624
2020 05: 596 x 39.72% x (155/15) x 50% x 8 x 744 x 40% x 85% x 80% = 1980148.53657
2020 06: 596 x 45% x (155/15) x 50% x 9 x 720 x 40% x 85% x 80% = 2442379.392
2020 07: 596 x 45% x (155/15) x 60% x 11 x 744 x 40% x 85% x 80% = 3701561.65632
2020 08: 596 x 45% x (155/15) x 60% x 13 x 744 x 40% x 85% x 80% = 4374572.86656
2020 09: 596 x 45% x (155/15) x 60% x 13 x 360 x 40% x 85% x 80% = 2116728.8064
The total capacity of HI36A0 is: 18419070.51 pieces, which means 18.419070 million pieces of Hi36A0 including its variants Hi36a0L/E.
All the above data is speculative; if it matches the actual data, it is just good luck. The author is Kurnal, please indicate when reprinting.